1. Field of the Invention
The present invention relates to an active matrix liquid crystal display (AMLCD) having active panels including thin film transistors (TFTs) and pixel electrodes arranged in a matrix pattern and a method of manufacturing the AMLCD, and more particularly, a method for reducing defects occurring at the source bus line and the source pad in a step of forming a double gate bus line of an AMLCD.
2. Description of the Related Art
Among various display devices displaying images on a screen, thin film type flat panel display devices are widely used because they are relatively thin and light weight. Particularly, a liquid crystal display is actively being developed and studied because the LCD provides a sufficiently high resolution and a sufficiently fast response time to display a motion picture.
The principle of the LCD uses optical anisotrophy and polarization property of liquid crystal materials. The liquid crystal molecules are relatively thin and long having orientation and polarization properties. Using these properties, the orientation in which the liquid crystal molecules are arranged can be controlled by applying an external electric field. Depending on the orientation of the liquid crystal molecules, light is allowed to either pass through the liquid crystal or is prevented from passing through the liquid crystal. A liquid crystal display effectively uses this characteristic behavior of liquid crystal.
Recently, AMLCDs which include TFTs and pixel electrodes arranged in a matrix pattern have received much attention because they provide enhanced picture quality and natural colors.
The structure of a conventional liquid crystal display is described below. The conventional liquid crystal display includes two panels each having many elements disposed thereon, and a liquid crystal layer formed between the two panels. The first panel (or color filter panel) located at a first side of the conventional liquid crystal display includes red (R), green (G), and blue (B) color filters sequentially arranged to correspond with an array of pixels disposed on a transparent substrate of the first panel. Between these color filters, a black matrix is arranged in a lattice pattern. A common electrode is formed and disposed on the color filters.
On the other side or second side of the conventional liquid crystal display, the second panel (or active panel) includes a plurality of pixel electrodes which are located at positions corresponding to the positions of pixels and are disposed on a transparent substrate. A plurality of signal bus lines are arranged to extend in the horizontal direction of the pixel electrodes, whereas a plurality of data bus lines are arranged to extend in the vertical direction of the pixel electrodes. At a corner of the pixel electrode, a thin film transistor is formed to apply an electric signal to the pixel. The gate electrode of the thin film transistor is connected to a corresponding one of the signal bus lines (or gate bus lines), and the source electrode of the thin film transistor is connected to a corresponding one of the data bus lines (or source bus lines). The end portions of the gate and source bus lines include terminals or pads for receiving signals applied externally thereto.
The above described first and second panels are bonded together and arranged to face each other while being spaced apart by a predetermined distance (known as a cell gap) and a liquid crystal material is injected between the two panels into the cell gap.
The manufacturing process for the conventional liquid crystal panel is rather complicated and requires many different manufacturing steps. Particularly, the active panel having TFTs and pixel electrodes requires many manufacturing steps. Therefore, it is beneficial to reduce the manufacturing steps to reduce the possible defects which may occur during the manufacture of the active panel and to reduce the time, expense and difficulty involved in manufacturing the liquid crystal display.
In a conventional method of manufacturing an active panel, aluminum or its alloy of low electric resistance material is used to form the gate bus line and the gate electrode and the surface of the aluminum is anodized to prevent hill-lock, thereby forming an anodic oxide film. As a result, the method required at least 8 masking steps.
However, a subsequent development in the method of manufacture has resulted in the reduction in the number of required masking steps. For example, after forming gate bus lines and gate electrodes, the surface of the aluminum is covered with a metal layer such as chromium or molybdenum instead of anodizing. Therefore, the total number of masking steps is reduced by one or two masking steps by eliminating the anodizing step and cutting the shorting bar for providing the electrode of the anodizing.
The conventional method of manufacturing the active panel is described in more detail with reference to FIGS. 1-4d. FIG. 1 is a plan view showing a conventional active panel. FIGS. 2a-2d are cross-sectional views showing the TFT taken along line IIxe2x80x94II in FIG. 1. FIGS. 3a-3d are cross-sectional views showing the gate pad and shorting bar taken along line IIIxe2x80x94III in FIG. 1. FIGS. 4a-4d are cross-sectional views showing the source pad taken along line IVxe2x80x94IV in FIG. 1.
On a transparent substrate 1, aluminum or aluminum alloy is vacuum deposited and patterned by photo-lithography to form a low resistance gate bus line 13a (FIG. 3a). Then, chromium or chromium alloy is vacuum deposited on the surface of the aluminum or aluminum alloy including the low resistance gate bus line 13a and patterned to form a gate electrode 11 and gate pad 15 (FIG. 2a). At this time, a gate bus line 13 is formed by patterning the chromium layer to completely cover the low resistance gate bus line 13a (FIG. 3b).
Next, an insulating material such as silicon oxid (SixOy) and silicon nitride (SixNy) is vacuum deposited on the surface including the gate bus line 13 to form a gate insulating layer 17 (FIG. 4a). Then, a semiconductor material such as an amorphous silicon and a doped semiconductor material such as impurity doped silicon are sequentially deposited on the insulating layer 17. The semiconductor material and the doped semiconductor material are etched at all locations except for an active area above the gate electrode 11 to form a semiconductor layer 35 and a doped semiconductor layer 37 seen in FIG. 2b. In this step of removing the semiconductor material and the doped semiconductor material, the semiconductor material and the doped semiconductor material located at portions corresponding to locations where a source pad and a source bus line are to be formed, are removed.
Next, chromium or chromium alloy is vacuum deposited on the surface including the doped semiconductor layer 37 and patterned to form a source electrode 21, a drain electrode 31, a source bus line 23 and a source pad 25. The source electrode 21 and the drain electrode 31 are formed over the gate electrode 11 and separated from each other by a desired distance. Using the source electrode 21 and the drain electrode 31 as a mask, the exposed portion of the doped semiconductor layer 37 between the source 21 and drain electrode 31 is removed (FIG. 2c). The source bus line 23 connects the source electrodes 31 in a row direction (FIG. 1) and the source pad 25 is formed at the end portion of the source bus line 23 (FIG. 4b).
An insulating material such as silicon oxide and silicon nitride is vacuum deposited on the surface including the source electrode 21, drain electrode 31 and the source pad 25 to form a protection layer 41 (FIG. 2d). Then, part of the protection layer is removed by patterning to form a drain contact hole 71 (FIG. 2d). At the same time, part of the protection layer 41 covering the source pad is removed to form a source pad contact hole 61 (FIG. 4c) and part of the protection layer 41 and the gate insulating layer 17 are removed to form a gate pad contact hole 51 (FIG. 3c).
Next, indium tin oxide is vacuum deposited on the surface including the protection layer 41 and patterned to form a pixel electrode 33, a source pad connecting terminal 67 and a gate pad connecting terminal 57. The pixel electrode 33 is connected with the drain electrode 31 through the drain contact hole 71 (FIG. 2e). The source pad connecting terminal 67 is connected with the source pad 25 through the source pad contact hole 61 (FIG. 4d). The gate pad connecting terminal 57 is connected with the gate pad 15 through the gate pad contact hole 51 (FIG. 3d).
As described above, the structure of the gate pad of the active panel formed by a conventional method includes a gate pad made of aluminum and a gate pad connecting terminal made of indium tin oxide which is connected with the gate pad through a gate pad contact hole. The structure of the source pad includes a source pad made of chromium and a source pad connecting terminal made of indium tin oxide which is connected with the source pad through the source pad contact hole. Thus, since the source pad is made of chromium, during the various process steps for forming the active panel, cracks may be formed in the source pad which causes line disconnection and thereby causes defects in the active panel of the liquid crystal display.
To overcome the problems described above, the preferred embodiments of the present invention provide a liquid crystal display and a method of manufacturing a liquid crystal display for preventing line disconnection at a source pad during manufacturing to thereby reduce defects in the active panel and increase the production yield of the manufacturing process.
According to one preferred embodiment of the present invention, a liquid crystal display includes a dummy source pad and a dummy source bus line to protect the source pad and to prevent line disconnection at the source pad.
According to another preferred embodiment of the present invention, a method of manufacturing a liquid crystal display, includes the steps of: forming a gate bus line on a substrate using a first conductive material thereon; forming an insulating layer on the substrate including the gate bus line by depositing an insulating material; forming a semiconductor layer, a doped semiconductor layer and a dummy source pad on the substrate including the gate insulating layer by depositing and patterning a semiconducting material and a doped material such as an impurity doped material; forming a source bus line and a source pad covering the dummy source pad on the substrate including the semiconductor layer, the doped semiconductor layer and the dummy source pad by depositing and patterning a second conductive material.
Further features, advantages and details of the present invention will become apparent from the detailed description of preferred embodiments provided hereafter. However, it should be understood that the description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
These and other elements, features, and advantages of the preferred embodiments of the present invention will be apparent from the following detailed description of the preferred embodiments of the present invention, as illustrated in the accompanying drawings.